1. Field of the Invention
Generally, the subject matter disclosed herein relates to integrated circuits, and, more particularly, to contact features for connecting contact areas or metal regions of semiconductor devices with conductive lines or regions, such as metal lines, in a higher wiring level of the semiconductor device, wherein the contact features are formed on the basis of advanced photolithography techniques.
2. Description of the Related Art
The fabrication of microstructures, such as integrated circuits, requires tiny regions of precisely controlled size to be formed in one or more material layers of an appropriate substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate or other suitable carrier materials. These tiny regions of precisely controlled size are typically defined by patterning the material layer(s) by applying lithography, etch, implantation and deposition processes and the like, wherein, typically, at least in a certain stage of the patterning process, a mask layer may be formed over the material layer(s) to be treated to define these tiny regions. Generally, a mask layer may consist of or may be formed by means of a layer of photoresist that is patterned by a lithographic process, typically a photolithography process. During the photolithography process, the resist may be spin-coated onto the substrate surface and then selectively exposed to ultraviolet radiation through a corresponding lithography mask, such as a reticle, thereby imaging the reticle pattern into the resist layer to form a latent image therein. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist. Based on this resist pattern, actual device patterns may be formed by further manufacturing processes, such as etch, implantation and anneal processes and the like. Since the dimensions of the patterns in sophisticated integrated microstructure devices are steadily decreasing, the equipment used for patterning device features have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. In this respect, resolution is considered as a measure for specifying the consistent ability to print minimum size images under conditions of predefined manufacturing variations. One important factor in improving the resolution is the lithographic process, in which patterns contained in the photo mask or reticle are optically transferred to the substrate via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus and wavelength of the light source used.
The resolution of the optical patterning process may, therefore, significantly depend on the imaging capability of the equipment used, the photoresist materials for the specified exposure wavelength and the target critical dimensions of the device features to be formed in the device level under consideration. For example, gate electrodes of field effect transistors, which represent an important component of modern logic devices, may have a length of 50 nm and less for currently produced devices, with significantly reduced dimensions for device generations that are currently under development. Similarly, the line width of metal lines provided in the plurality of wiring levels or metallization layers may also have to be adapted to the reduced feature sizes in the device layer in order to account for the increased packing density. Consequently, the actual feature dimensions may be well below the wave-length of currently used light sources provided in current lithography systems. For example, currently, in critical lithography steps, an exposure wavelength of 193 nm may be used, which, therefore, may require complex techniques for finally obtaining resist features having dimensions well below the exposure wavelength. Thus, highly non-linear processes are typically used to obtain dimensions below the optical resolution. For example, extremely non-linear photoresist materials may be used, in which a desired photochemical reaction may be initiated on the basis of a well-defined threshold so that weakly exposed areas may not substantially change at all, while areas having exceeded the threshold may exhibit a significant variation of their chemical stability with respect to a subsequent development process.
The usage of highly non-linear imaging processes may significantly extend the capability for enhancing the resolution for available lithography tools and resist materials.
Due to the complex interaction between the imaging system, the resist material and the corresponding pattern provided on the reticle, even in highly sophisticated imaging techniques, which may possibly include optical proximity corrections (OPC) and the like, the consistent printing of latent images, that is, of exposed resist portions, which may be reliably removed or maintained, depending on the type of resist used, may also significantly depend on the specific characteristics of the respective features to be imaged. For instance, it has been observed that line-like features having a specific design width and a design length may require specific exposure recipes for otherwise predefined conditions, such as a specified lithography tool in combination with a specific reticle and resist material, in order to reliably obtain the desired critical width dimension, while the length dimension is less critical, except for respective end portions, so-called end caps of the respective lines, which may also typically require respective corrections. Consequently, for other features having critical dimensions in two lateral directions, such as substantially square-like features, the same exposure recipe as used for line-like features may not be appropriate and may, therefore, require elaborated process parameters, for instance with respect to exposure dose and OPC, and the like. Furthermore, the respective process parameters in such a highly critical exposure process may have to be controlled to remain within extremely tight process tolerances compared to a respective exposure process based on line-like features, which may contribute to an increasing number of non-acceptable substrates, especially as highly scaled semiconductor devices are considered. Due to the nature of the lithography process, the corresponding process output may be monitored by respective inspection techniques in order to identify non-acceptable substrates, which may then be marked for reworking, that is, for removing the exposed resist layer and preparing the respective substrates for a further lithography cycle. However, lithography processes for complex integrated circuits may represent one of the most dominant cost factors of the entire process sequence, thereby requiring a highly efficient lithography strategy to maintain the number of substrates to be reworked as low as possible. Consequently, the situation during the formation of sophisticated integrated circuits may become increasingly critical with respect to throughput.
With reference to FIGS. 1a-1c, a typical process sequence for forming vias or contacts and line-like features may be described in order to more clearly demonstrate the problems involved in the manufacturing process for forming advanced semiconductor devices.
FIG. 1a schematically illustrates a top view of a semiconductor device 100 in a manufacturing stage after a respective lithography process including a respective development step. The semiconductor device 100 may comprise a resist layer 110, which may be formed above a respective material layer, as will be described later on with reference to FIG. 1b. The resist layer 110 has formed therein respective resist openings 110A having lateral dimensions in a length direction L and a width direction W, indicated as 110L, 110W. The respective lateral dimensions 110L, 110W may be similar if, for instance, a substantially square-like feature is to be formed on the basis of the resist openings 110A. As previously explained, for highly sophisticated applications, the corresponding lateral dimensions 110L, 110W may represent critical dimensions for the device layer under consideration, i.e., these lateral dimensions may represent the minimum dimensions to be printed in the corresponding device level. The respective resist openings 110A are to be used as etch masks for patterning the underlying material layer in order to form respective openings therein that, in turn, may be used for forming appropriate device features, such as contacts, vias and the like, which may provide contact to overlying and underlying device features, such as metal regions, metal lines and the like. For example, it may be assumed that a connection to a respective line feature is to be provided in a subsequent device level, wherein it may be assumed that the corresponding line features, indicated by dashed lines, may have substantially the same critical dimension in the width direction W.
FIG. 1b schematically illustrates the semiconductor device 100 in a cross-sectional view taken along the line Ib-Ib from FIG. 1a. The semiconductor device 100 in this manufacturing stage comprises a substrate 101, which may represent an appropriate carrier material including the respective material layers (not shown) which may comprise device features, such as transistors, capacitors and the like. Furthermore, a dielectric layer 102 comprised of any appropriate dielectric material, such as silicon dioxide, silicon nitride, combinations thereof and the like, is formed above the substrate 101 and comprises a respective opening 102A having similar lateral dimensions as the respective resist opening 110A. Furthermore, a further dielectric layer 103, for instance an anti-reflective coating (ARC) layer and the like, may be formed on the dielectric layer 102 in order to assist the respective exposure process for patterning the resist layer 110. The layer 103 may be formed of any appropriate material, such as silicon oxynitride, silicon nitride and the like.
The semiconductor device 100 as shown in FIG. 1b may be formed on the basis of the following processes. After providing respective device features in and above the substrate 101, the dielectric layer 102 may be deposited on the basis of well-established manufacturing techniques, which may comprise chemical vapor deposition (CVD) processes and the like. For instance, sophisticated CVD techniques for forming silicon nitride, silicon dioxide and the like are well established in the art, for instance, for providing a reliable encapsulation of respective device features, such as transistors and the like. After the deposition of the layer 102, a respective planarization process may be performed, if required, to enhance the surface topography prior to forming the layer 103 and the resist layer 110. In other cases, the respective surface topography may be maintained and may be taken into account by appropriately forming the resist layer 110. The resist layer 110 may be prepared for a subsequent exposure process on the basis of established treatments, such as pre-exposure bake and the like, to enhance process uniformity. Thereafter, the resist layer 110 may be exposed on the basis of a respective photomask or reticle, which may comprise corresponding mask features that may possibly be designed on the basis of appropriate correction techniques in order to take into account the respective non-linearity of the corresponding exposure process, as previously described. In other cases, any other appropriate techniques, such as phase shift masks and the like, may be used. During the exposure process, typically, a well-defined exposure field may be illuminated by an optical beam that is modulated by the pattern included in the reticle to transfer the reticle pattern into the resist layer 110 in order to define a respective latent image. That is, the latent image may be understood as a respective portion of the resist layer 110 receiving a significant amount of radiation energy in order to modify the photochemical behavior of the corresponding resist material. In the present case, it may be assumed that a positive resist may be used which may become soluble upon exposure during a subsequent development step. Consequently, during the respective exposure process, the substrate 101 is appropriately aligned and thereafter a certain exposure dose is transferred into the respective exposure field under consideration in order to create the respective latent images, wherein the mask features and/or the imaging techniques may be selected such that a certain threshold of energy for generating a required photochemical modification may be accomplished within specified areas according to the desired design dimensions of the respective features. That is, in the above-described case, the exposure process is designed in combination with respective mask features so as to deposit sufficient energy within an area corresponding to the openings 110A having the lateral dimensions 110L, 110W in order to obtain a substantially complete removal of the exposed resist material during the subsequent development step. Due to the minimum dimensions in both lateral directions, respective process parameters of the exposure process, such as exposure dose and the like, as well as of any pre-exposure and post-exposure processes, may have to be maintained within tightly set process margins in order to obtain the resist openings 110A since even some incompletely opened areas within the resist opening 110A may result in corresponding irregularities during the subsequent etch process for forming the openings 102A in the dielectric layer 102. Hence, after developing the exposed resist layer 110, i.e., after removing exposed portions of the resist material, an inspection of the substrate 100 may be performed in order to identify exposure fields outside the respective specifications. Due to the very tight process margins for forming the critical openings 110A, a corresponding high number of non-acceptable exposure fields, each of which may be exposed on the basis of an individually adjusted exposure dose, may occur in particular if highly scaled devices are considered, in which the respective lateral dimensions 110L, 110W may be approximately 100 nm and less.
FIG. 1c schematically illustrates the device 100 in a cross-sectional view according to the section Ic-Ic in FIG. 1a in an advanced manufacturing stage. Here, the opening 102A may be filled with an appropriate material, such as a metal, and a further dielectric layer 104 may be formed above the layer 102 which comprises a further line-like feature 104A. Furthermore, a resist layer 120, possibly in combination with a respective ARC layer 113, may be formed above the dielectric layer 104 including respective trench-like openings 120A having the lateral dimension 110W. In this case, it is assumed that the width of the resist opening 120A may substantially correspond to the critical dimensions of the resist openings 110A.
A respective process flow for forming and patterning the layers 104, 113 and 120 may comprise substantially the same process steps as described with reference to FIG. 1b. However, as previously explained, during the corresponding lithography sequence including any pre- and post-exposure processes, it has been observed that corresponding process tolerances may be less critical compared to the exposure process for forming the openings 110A, which is believed to be caused by the lack of respective boundary conditions in the lateral length direction L. For example, the respective resist opening 120A may be formed with a reduced exposure dose compared to the opening 110A, while also other process parameters may be less critical, thereby providing a moderately wider process window for the corresponding lithography process for forming the line-like features 120A.
Since respective resist openings 110A for contacts and vias may have to be provided at various manufacturing stages, the very tight process tolerances to be met may thus significantly contribute to a reduced overall throughput of the per se very cost intensive lithography module, which may, therefore, significantly contribute to overall production costs. Furthermore, the respective exposure processes may be restricted to highly advanced lithography tools only, thereby even more increasing the overall production costs. Furthermore, the fabrication of contacts on the basis of substantially circular cross-sections may contribute to significant yield losses due to patterning-related process fluctuations as described above, while also the contact resistance, for instance for connecting the very first metallization layer with the active semiconductor regions, is moderately high.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.